How to Design a PCB Layout for Highest Half-Bridge GaN Driver Performance
Abstract
This article highlights effective design practices for gallium nitride (GaN) half-bridge converters driven by a 100 V half-bridge GaN driver, focusing on reducing voltage ringing and enhancing thermal performance. This GaN driver is utilized to optimize the performance of GaN FETs by leveraging their advantages and providing robust overvoltage protection.
Introduction
In recent years, gallium nitride (GaN) technology has significantly transformed the semiconductor industry due to its advantages over traditional silicon MOSFETs, including reduced parasitic capacitance, the absence of a body diode, superior thermal efficiency, and a compact footprint.1 GaN devices have become increasingly reliable and capable of operating across a broad voltage range. They are now widely adopted to boost efficiency and power density in applications from consumer electronics to automotive power systems.
GaN devices require specialized drivers as they have many distinguishing electrical characteristics, such as low gate voltage limit and high reverse conduction loss during dead time. Due to performance issues and potential device damage, conventional silicon MOSFET drivers are not advised to drive GaN FETs without additional protection circuitries. Despite a growing market for GaN FETs, dedicated GaN drivers remain limited.
Recently, Analog Devices has developed its first 100 V half-bridge GaN driver, the LT8418. This advanced driver offers robust current sourcing and sinking capabilities and features an intelligent, integrated bootstrap switch to maintain a stable bootstrap voltage with minimal dropout from VCC. Furthermore, the device has split gate drivers, which enable fine control over the turn-on and turn-off slew rates, reducing ringing and optimizing electromagnetic interference (EMI) performance. These features make this IC ideal for demanding applications, including Class-D amplifiers, high efficiency data center power supplies, high frequency DC-to-DC converters, and motor drives.
However, GaN-based converters operating at high switching speed are particularly sensitive to ringing due to board parasitic elements. Overshooting or undershooting voltage can damage the FET if it exceeds the absolute maximum threshold. Therefore, it is essential to leverage optimal design practices in GaN applications with this new device to increase efficiency and improve performance.
Mitigate Parasitic Inductance
A rapid change in current during switching events causes parasitic inductance inherent in the PCB layout to resonate with stray capacitance, leading to ringing at various nodes in the converter. At a fast switching speed, the ringing is more pronounced due to the fast di/dt transient. In the half-bridge configuration, the primary contributors to this parasitic inductance are the power loop and gate loop, as shown in Figure 1.
Figure 1. Common parasitic inductance sources in a half-bridge configuration.
The power loop inductance consists of the FET drain inductance LD, the common-source inductance LCS, and parasitic inductance from input capacitors and PCB traces. The gate loop inductance includes the gate inductance LGATE and common-source inductance LCS.
Figure 2 and Figure 3 demonstrate the impact of parasitic inductance, showing more ringing on the switch node voltage and gate signal. This ringing at the switch node increases the switching loss and deteriorates the EMI performance. Meanwhile, the ringing on the gate signal can exceed the gate voltage threshold and absolute rating, resulting in a false turn-on/turn-off of the FET and permanent damage to the gate. Therefore, it is critical to minimize the parasitic inductance in a GaN converter to ensure robust operation.
Figure 2. Ringing on the switch node voltage due to hot loop parasitic inductance.
Figure 3. Ringing on the gate signal due to gate loop parasitic inductance.
Internal Vertical Layout Minimizes Hot Loop Inductance
Minimizing the hot loop inductance in a buck or boost is essential to mitigate the inductive effect and associated voltage spikes during fast dv/dt transitions, resulting in improved efficiency and enhanced EMI performance. The hot loop layout defined by the position of GaN FETs and hot loop capacitors is crucial as it determines the physical dimensions of the hot loop and, consequently, its inductance. The internal vertical layout illustrated in Figure 4 is recommended for minimal hot loop inductance.2
Figure 4. Optimal layout—internal vertical with FETs and hot loop capacitors on the same layer.
In this layout, the high-side and low-side FETs are placed side by side on the same PCB layer. The parallel placement minimizes the length of interconnecting traces. Multiple hot loop capacitors (ceramic capacitors with low equivalent series resistance (ESR)) are also placed on the same layer and directly adjacent to the FETs’ source and drain terminals. This layout utilizes the first internal layer as the power loop return path, which is in close proximity to the forward path on the top layer, resulting in the minimal hot loop’s physical size. It also ensures that the hot loop stray inductance is independent of the total board thickness. Moreover, the induced magnetic fields of the forward and return currents cancel each other out, further reducing the parasitic inductance.2
Hot Loop Capacitor Position for Optimal Thermal Performance
Due to their compact size and limited contact area, GaN devices can experience extreme thermal stress at high switching frequencies and high loads. Therefore, effective thermal management practices are essential when designing the PCB layout to ensure reliable performance.
In a buck converter configuration, the top FET typically experiences the highest temperature due to the losses from hard switching. To enhance heat dissipation, it is recommended to position high frequency hot loop capacitors closer to the bottom FET. This placement not only optimizes the electrical path for the high frequency loop but also provides additional space around the top FET, allowing for improved thermal dissipation. In this layout, the power plane on the first internal layer, underneath Q1 and Q2, is VIN. The top layer of this layout strategy is shown in Figure 5a.
In contrast, for a boost configuration, the bottom FET usually undergoes higher thermal stress due to hard switching. Consequently, the high frequency hot loop capacitors should be located near the top FET, leaving room around the bottom FET to improve its thermal dissipation. The return ground plane is on the second layer. This layout is depicted in Figure 5b.
Figure 5. Hot loop capacitor placement for thermal dissipation improvement in buck and boost: (a) Buck layout with capacitors near bottom FET; (b) Boost layout with capacitors near top FET.
Vias Are Tiny but Useful
Placing multiple interlayer connection vias directly on the FET’s solder pads helps reduce the hot loop parasitic inductance further, as shown in Figure 6. Current flows through these vias in opposite directions due to the interleaving drain and source terminals, forming multiple opposing adjacent magnetic field loops. These magnetic loops lead to magnetic field self-cancellation, significantly reducing the parasitic inductance in the hot loop.2
In addition, these vias are used to effectively enhance thermal performance. They transfer the thermal energy from the FET to copper planes on other PCB layers. This helps maintain the device’s thermal integrity during high power operation. The vias also distribute the current across multiple PCB layers and minimize resistance. It is advised to fill these vias to prevent outgassing during soldering, as well as solder leakage, and increase both thermal and electrical conduction.
Figure 6. Vias were placed on the solder pads of GaN devices for thermal and electrical conductivity improvement.
Figure 7 compares the thermal differences between two GaN-based buck circuit boards driven by the LT8418. Under identical operating conditions, the GaN FETs on the board designed with the recommended layout practices remain significantly cooler (up to 28˚C) than those on the counterpart board.
Figure 7. Thermal comparison at VIN = 48 V, VOUT = 12 V, IOUT = 10 A, FSW = 500 kHz. Proposed design practices help reduce FET temperature by almost 30˚C: (a) Layout with poor design practices—high FET temperatures; (b) Layout with proposed design practices—cool FET temperatures.
Gate Resistors Are Your Friend
GaN FETs have inherently lower absolute maximum gate voltage ratings, commonly around 6 V, compared to silicon (Si) MOSFETs.3 Consequently, conventional Si MOSFET drivers are not recommended for driving GaN devices as they are designed for higher gate voltage. Thus, care must be taken when designing GaN converters to prevent damage due to voltage spikes or ringing on the gate.
Switching GaN FETs at excessively high speeds can result in significant voltage overshoot and oscillation at the switch node. As mentioned, this is primarily caused by parasitic inductances and capacitances within the circuit. Moreover, the coupling between the switch node and the gate can induce unintended oscillations, potentially triggering false turn-on events in the FET. Such inadvertent turn-on can lead to shoot-through conditions, where both high-side and low-side FETs conduct simultaneously, causing excessive current flow. This phenomenon not only degrades system efficiency but also poses a serious risk of thermal over-stress and permanent damage to the FETs. Mitigating this issue by adjusting the gate signal’s slew rate is crucial for ensuring the reliability and longevity of the circuit.
The LT8418 is designed to drive GaN devices with a gate voltage ranging from 3.85 V to 5.5 V, allowing a good safety margin at the gate. The GaN FET should be placed as close to the IC as possible to keep the gate trace short, minimizing the gate inductance. Furthermore, this GaN driver has split gate drives enabling independent adjustment of the turn-on and turn-off slew rate by using gate resistors. This feature enables fine-tuning of switching behavior to match system requirements. Gate resistors are utilized to dampen oscillations in the gate signal by dissipating the energy of high frequency ringing. The gate resistor values should be selected carefully to balance the switching speed, EMI performance, and gate loss.
Figure 8. Waveforms of a buck with adequate and inadequate top gate resistor values: (a) RTGP = 2 Ω – Clean waveforms with minimal ringing; (b) RTGP = 1 Ω – Oscillating waveforms exceeding gate max rating.
A good practice for choosing the optimal gate resistor value is to evaluate the gate signal on the bench in the worst-case conditions such as maximum load and highest switching voltage. Begin testing with a higher gate resistor value, such as 3.3 Ω, to help dampen any initial ringing and ensure a safe baseline. Reduce the resistance incrementally while monitoring for excessive ringing, overshoot, or undershoot on the gate signal. Ensure the gate voltage waveform has sufficient safety margins below the maximum rated gate voltage and above the threshold voltage. This method optimizes the resistor value for acceptable signal quality and efficiency while maintaining adequate damping.
Figure 8a shows some typical waveforms of a buck with an optimal top gate resistor of 2 Ω. The waveforms are clean, with no significant overshoot or ringing. This indicates effective damping and optimized switching characteristics. In contrast, Figure 8b highlights the overshoot on the top gate signal exceeding the safe threshold of 6 V because of the inadequate top gate resistor (1 Ω). This can lead to potential damage to the GaN FET and increased EMI.
A Bad Test Point Layout Can Deceive You—Be Careful
A poorly designed test point layout can introduce parasitic inductance that distorts the observed signals, leading to false readings and potentially misleading conclusions about circuit performance. Thus, a proper test point layout is crucial for measuring accurate gate signals, especially at fast switching speeds.
One of the key practices for designing test points is to use the short Kelvin connection. This approach separates the desired reading signal from other noisy signals. It minimizes the impact of shared parasitic elements and ensures the probe measures the true gate signal directly at the FET’s terminals.
For measuring the bottom gate and switch node signals, low capacitance passive probes with spring ground leads close to the GaN FET’s GND are recommended to minimize the impact of the probe’s physical connection. It is more difficult to read the top gate VGS signal as it is referenced to the switch node. A high speed differential probe suits this task. These optical differential probes typically require a dedicated MMCX connector, highlighted in Figure 9, for the best result.
The waveform comparison between an inadequate and proposed test point designs is also demonstrated in Figure 10.
Figure 9. An MMCX connector is recommended for a differential probe when reading gate signals.
Figure 10. Waveform comparison between a bad and a good test point design: (a) false ringing on waveforms induced by a bad test point layout; (b) clean waveforms captured from a good test point layout.
Conclusion
This article highlights key design practices for GaN half-bridge converters driven by the LT8418. Optimized PCB layouts, proper capacitor placement, and fine-tuned gate resistors ensure robust operation, while accurate measurement techniques verify performance. These practices, combined with the device’s advanced features, make it an ideal driver for high frequency applications demanding efficiency, compactness, and thermal stability.
(The views expressed in this article are by – Mr. Peter Pham, Senior Applications Engineer, and Mr. Sam Jafari, Applications Engineer, Analog Devices. Technuter.com doesn’t own any responsibility for it.)
