Xilinx Accelerates System Verification with Vivado Design Suite 2015.1

Bangalore, India, May 3, 2015: Xilinx has announced acceleration of system verification with the release of the Vivado Design Suite 2015.1, featuring major  productivity advances  for the development and deployment of  All Programmable FPGAs and SoCs. This release includes the Vivado Lab Edition, accelerated Vivado Simulator and third party simulation flows, interactive clock domain crossing (CDC) analysis, and advanced system performance analysis with the Xilinx Software Development Kit (SDK). 

New Vivado Lab Edition

The Vivado Lab Edition is a no-cost, lightweight programming and debug edition of the Vivado Design Suite. The Lab Edition includes the Vivado Device Programmer, Vivado Logic and Serial I/O Analyzer, as well as memory debug tools. It is intended for use in lab environments where the full-featured Vivado Design Suite is not required.  The Vivado Lab Edition is 75 percent smaller than the complete Vivado Design Edition, which considerably reduces lab set-up time and system memory requirements. For design teams that require remote debug or programming over Ethernet, the Vivado Design Suite 2015.1 also provides a standalone hardware server, which is less than 1 percent of the complete Vivado Design Edition. 

Vivado Simulator and Third Party Simulation Flows

The Vivado Design Suite 2015.1 also features advancements in the simulation flows that reduce the LogiCORE IP compile times by over 2x. As a result, overall simulation performance is 20 percent faster compared to previous releases. The release also includes fully-integrated simulation flows with Alliance Program members, Aldec, Cadence Design Systems, Mentor Graphics and Synopsys.

“Leveraging the Xilinx Vivado Tcl store infrastructure, Aldec now provides full integration for Riviera-PRO and Active-HDL within the Vivado Design Suite” said Dr. Stanley Hyduke CEO of Aldec Inc. “This unique integration capability results in a fantastic ease of use advantage for our customers.” 

Interactive Clock Domain Crossing Analysis

Xilinx has also extended its advanced verification portfolio by offering an interactive CDC analysis capability. This feature improves productivity by enabling the debug of CDC issues earlier in the design, reducing expensive in-system debug cycles. Combined with the Vivado Design Suite’s interactive timing analysis and cross-probing features, the CDC analysis capability provides powerful timing analysis and debug functionalities, accelerating time to market. 

Xilinx Extends SDK with Advanced In-system Performance Analysis and Validation

To accelerate the development of the Zynq-7000 All Programmable SoC, Xilinx has extended its system performance and analysis toolbox for bare metal and Linux applications. The Xilinx SDK now provides embedded software developers the ability to analyze the performance and the bandwidth of their SoC design, including key performance metrics for the processor subsystem (PS) as well as bandwidth analysis between the PS, the Programmable Logic (PL) and external memories. System modeling designs using AXI traffic generators are provided for the Zynq-7000 All Programmable SoC ZC702 and ZC706 evaluation boards. 


The Vivado Design Suite 2015.1 is available now with support for Xilinx’s 7 series FPGAs and SoCs and UltraScale devices.

© Technuter.com News Service

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